1. Field of the Invention
This invention relates generally to high performance transistor devices and, more particularly, to low threshold voltage transistors. Specifically, the present invention relates to low Vt semiconductor devices having improved implanted well structure which permits short channel design while substantially reducing punch through characteristics, reduced threshold variation and high mobility.
2. Discussion of the Related Art
As the semiconductor industry has advanced, the sizes of active semiconductor transistor devices have shrunk to sub-micron dimensions. This has required the formation of devices that push the limits of known manufacturing techniques and processes. Semiconductor devices formed with a short channel length are particularly affected by manufacturing process variations. For example, short channel MOS (Metal Oxide Semiconductor) transistor devices can be difficult to manufacture with acceptable threshold voltage (Vt) control.
In a MOS transistor, the threshold voltage is the voltage or potential that must be applied to the gate region of the transistor before a current will flow in the channel below the gate region between the source and drain. In general, higher threshold voltages are undesirable because higher power supplies are required for operating the semiconductor devices. In addition, with higher threshold voltages, the semiconductor devices are slower. As power supply voltage decreases, analog circuitry can be adversely affected as the devices are stacked between Vdd and Vss. Moreover, this loss of "headroom" reduces the available voltage swing. Moreover, if the threshold voltage of an access device for a memory cell is too high, then it is more difficult to write data into the cell.
As MOS technology has evolved, the supply voltage (Vdd) has also scaled with the size of the devices. For example, as channel lengths have decreased, the supply voltages have correspondingly decreased. In many applications, it is desirable to provide lower supply voltages for given device sizes. This is because devices requiring lower supply voltages generally conserve power, a feature which is particularly desirable in systems which dissipate large amounts of energy or rely on limited power sources such as batteries. However, there has been some concern about the effects of low supply voltage on device performance.
In circuits made up of conventional MOS devices, the relationship of maximum frequency, or the performance of the circuit, to supply voltage and threshold voltage is governed by the long and short channel effects of the component MOS devices. It has been found that the performance of a circuit made up of truly long channel devices is dependent on the absolute value of the supply voltage. Consequently, if the supply voltage to the devices in such circuits is lowered, then performance is also lowered. However, in circuits made up of truly short channel devices, performance is governed by the ratio of threshold voltage to supply voltage. This means that in such circuits, the supply voltage can be lowered with no loss in performance so long as the threshold voltage is also lowered to maintain a constant Vt/Vdd ratio.
Thus, while low threshold voltage MOS devices appear to be desirable, there have been certain problems associated with such devices in the past. First, as the threshold voltage is lowered, the drain-to-source leakage current of the transistor increases. Leakage current is that current which flows across the channel region when the transistor is turned off. In applications where the device must frequently switch, such as in microprocessors, this does not cause a problem. However, in other applications where the device is normally inoperative or inactive, such as in memory devices, this is a significant problem. Moreover, in short channel devices having a low threshold voltage, the distance between the drain and source regions is very small, and if this distance becomes too small, the depletion regions of the source and drain in the channel region can overlap to cause punch through. When this occurs, current flows through the path between the source and drain created by the depletion regions overlapping even when the transistor is turned off. In such instances, the gate control of the channel is lost.
There have been numerous attempts to develop transistor devices which overcome the aforementioned problems. Some examples of these efforts are illustrated in U.S. Pat. No. 5,493,251, U.S. Pat. No. 5,529,940, U.S. Pat. No. 5,589,701, U.S. Pat. No. 5,661,045, U.S. Pat. No. 5,622,880 and U.S. Pat. No. 5,719,422. It is known that the threshold voltage of a short channel MOS device is very sensitive to the dopant concentration of the substrate of the device. As a result, many approaches used to form low threshold devices rely on counterdoping the "standard" threshold devices, resulting in significant mobility degradation. Conversely, approaches that rely on "natural" or very low doping levels suffer from short channel Vt rolloff or punch through. It is also known that the variation of the threshold voltage is affected by the number of implant steps required to set the Vt. Hence, counter-doped devices have higher variability. Moreover, in both high and low threshold voltage devices, it is known that a buried electrode region of relatively high dopant concentration will help to suppress growth of depletion regions and thereby reduce punch through. However, there is still a need for an improved high performance, short channel transistor device having a low threshold voltage which experiences little if any punch through characteristics while maintaining high mobility and low threshold variation.